Integrated circuits are generally fabricated on a thin, circular silicon wafer or substrate. Semiconductor devices and electrical interconnections that form the integrated circuit are conventionally made by building many mask layers on top of one another on the substrate. Each successive mask layer may have a pattern that is defined using a mask. A mask has a shape used for processing features in a particular process step during fabrication. The mask layers are fabricated through a sequence of pattern definition steps using the masks, which are interspersed with other process steps such as oxidation, etching, doping and material deposition. When a mask layer is defined using a mask chosen or provided by a customer, the mask layer is programmed or customized.
The lowest, “base” layers include the active areas of the semiconductor devices, such as diffusion regions and gate oxide areas, and desired patterns of the polysilcon gate electrodes. One or more metal and insulating layers are then deposited on top of the base layers and patterned to form conductive segments, which interconnect the various semiconductor devices formed in the base layers. Electrical contacts or vias are formed to electrically connect a conductive segment of one of the metal layers with a conductive segment or semiconductor device on one of the other layers on the wafer.
Higher-level logic functions, such as phase-locked loops, are typically implemented as standard cells so they can be optimized for a desired operating frequency range. It is therefore common for ASIC vendors to include several versions of a phase-locked-loop cell, each with different operating characteristics, in a cell library so that the appropriate cell can be selected an instantiated in a design for a particular application. However, each PLL cell may have different base layer and metal layer patterns since they are implemented as standard cells. This increases the design and fabrication cycle times since the base layer masks and lower metal layer masks may change depending upon which PLL cell is selected. Also, once the integrated circuit is fabricated, the frequency range of the PLL is fixed. This leaves the end user of the integrated circuit with no flexibility to change the frequency range of the PLL.
Phase-locked loop cells are therefore desired, which allow selection of the frequency range after fabrication and for reduction in the design and fabrication cycle times associated with the implementation of these cells on a integrated circuit.